# Timer counts and interrupt period
# Scope: Ideal timer overflow interval; divider and counter width supplied.
# Status: illustrative worked example; engineering review pending.
# Inputs are example values. Checks are editable example requirements, not standards.

clock = 48000000 Hz
prescaler = 48
bits = 16

tick := prescaler/clock [s]
overflow := tick*2^bits [s]

check overflow interval target: overflow >= 0.05 s

scenario alternative: clock = 3.84e+07 Hz